written 2.8 years ago by | • modified 2.6 years ago |

**Subject:** VLSI Design

**Topic:** Data Path Design

**Difficulty:** Medium

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Write short notes on: Array multiplier

written 2.8 years ago by | • modified 2.6 years ago |

**Subject:** VLSI Design

**Topic:** Data Path Design

**Difficulty:** Medium

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written 2.6 years ago by |

- An interesting example of NORA circuit is a series – parallel multiplier which accepts one word in parallel format and multiplies it by a second word that is in a series format.
- Consider 2 4-bit words,

a = a0 a1 a2 a3; b = b0 b1 b2 b3

standard binary product (axb) is calculated by -

Where individual terms are given by expression –

P0 = a0b0

P1 = a0b1 + a1b0 +c0

P2 = a0b2 + a1b1 + a2b0 + c1

P3 = a0b3 + a1b2 + a2b1 + a3b0 + c2

P4 = a1b3 + a2b2 + a3b1 + c3

P5 = a2b3 + a3b2 + c4

P6 = a3b3 + c5

P7 = c6

For each of the product bits Pi (i = 0 to 7), ‘+’ represents binary addition and Cn-1 is the carry bit from the Pn addition. The multiplication can be summarized by

Now construct a 4-bit series-parallel multiplier that uses an input word a = a0 a1 a2 a3 and multiplies it by bits of second word b = b0 b1 b2 b3, one bit at a time i.e. first b0 the b1 and so on. As each b-bit is provided, multiplier calculates the product (a3 a2 a1 a0) x bi This yields the individual products

These are all the terms required in the product. Adding each column will give the product terms in order from right (P0) to left (P7).

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